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| d a t a sh eet product speci?cation supersedes data of 2001 may 29 file under integrated circuits, ic02 2001 aug 15 integrated circuits TDA8020hl dual smart card interface
2001 aug 15 2 philips semiconductors product speci?cation dual smart card interface TDA8020hl features two independent 6 contacts smart card interfaces supply voltage to the cards; v cc =5or3v 5%; i cc up to 65 ma integrated dc/dc converter (doubler, tripler or follower) for allowing power supply from 2.5 to 6.5 v independant supply voltage for interface signals (from 1.5 to 6.5 v) control and status via the i 2 c-bus four possible devices in parallel due to two i 2 c-bus address pins electrical specifications according to iso 7816 or emv norms automatic activation and deactivation sequences by means of integrated sequencers automatic clock count and reset toggling during warm or cold reset interrupt request output to the controller 6 kv esd protection on cards contacts automatic emergency deactivation in the event of supply drop-out, overload, overheating or card take-off current limitation on pins clk, rst, i/o and v cc integrated voltage supervisor for power-on reset and drop-out detection power-down mode with several wake-up events. applications set top boxes banking terminals internet terminals. general description the TDA8020hl is a one-chip dual smart card interface. controlled by the i 2 c-bus, it guarantees conformity to iso 7816 or emv norms with very few external components. ordering information type number package name description version TDA8020hl lqfp32 plastic low pro?le quad ?at package; 32 leads; body 7 7 1.4 mm sot358-1 2001 aug 15 3 philips semiconductors product speci?cation dual smart card interface TDA8020hl quick reference data note 1. both cards are not allowed to operate at maximum current at the same time at minimum supply voltage. symbol parameter conditions min. typ. max. unit v dd supply voltage on pins v dd and v dda 2.5 - 6.5 v v ddi supply voltage for interface signals 1.5 - v dd v i dd supply current (i dd and i dda )v dd = 3.3 v; inactive mode -- 150 m a v dd = 3.3 v; power-down mode; 2 cards activated; v cc1 =v cc2 =5v; i cc1 =i cc2 = 100 m a; clk1 and clk2 stopped -- 2ma v dd = 3.3 v; active mode; v cc1 =v cc2 =5v; i cc1 +i cc2 =80ma; clk1 = clk2 = 5 mhz -- 400 ma v dd = 3.3 v; active mode; v cc1 =v cc2 =3v; i cc1 =i cc2 =10ma; clk1 = clk2 = 5 mhz -- 80 ma v cc1 , v cc2 supply voltage for card 1 and 2 note 1 5 v card 4.75 - 5.25 v 3 v card 2.80 - 3.20 v i cc1 , i cc2 supply current for card 1 and 2 0 - 55 ma v th1 threshold voltage for the supervisor on v dd 2.1 - 2.4 v v hys1 hysteresis on v th1 50 - 100 mv t amb ambient temperature - 25 - +85 c 2001 aug 15 4 philips semiconductors product speci?cation dual smart card interface TDA8020hl block diagram handbook, full pagewidth i 2 c-bus and registers level shifters internal oscillator supply supervisor voltage reference dc/dc converter clock circuitry sequencer1 TDA8020hl card1 drivers sap 20 14 19 15 17 16 13 3 5 4 2 32 1 9 11 10 8 6 7 12 18 31 28 27 26 29 25 22 21 24 23 30 v dd sam sbp sbm v dda v up c del irq sda sad0 sad1 scl agnd gnd clk1 rst1 v cc1 cgnd1 i/o1 pres1 clock circuitry sequencer2 card2 drivers clk2 rst2 v cc2 cgnd2 i/o2 pres2 v ddi i/o2uc clkin2 clkin1 i/o1uc fce834 fig.1 block diagram. 2001 aug 15 5 philips semiconductors product speci?cation dual smart card interface TDA8020hl pinning symbol pin description pres1 1 card 1 presence contact input (active high) cgnd1 2 ground connection output to card 1 (c5 contact) clk1 3 clock output to card 1 (c3 contact) v cc1 4 supply voltage output to card 1 (c1 contact); decouple to pin cgnd1 with 2 100 nf capacitors with esr < 100 m w rst1 5 reset output to card 1 (c2 contact) i/o2 6 i/o contact to card 2 (c7 contact); internal 15 k w pull-up resistance to pin v cc2 pres2 7 card 2 presence contact input (active high) cgnd2 8 ground connection output to card 2 (c5 contact) clk2 9 clock output to card 2 (c3 contact) v cc2 10 supply voltage output to card 2 (c1 contact); decouple to pin cgnd2 with 2 100 nf capacitors with esr < 100 m w rst2 11 reset output to card 2 (c2 contact) gnd 12 ground connection v up 13 output of dc/dc converter; a 220 nf capacitor with esr < 100 m w must be connected to pin agnd sap 14 capacitors connection for the dc/dc converter; a 220 nf capacitor with esr < 100 m w must be connected between pins sap and sam sbp 15 capacitors connection for the dc/dc converter; a 220 nf capacitor with esr < 100 m w must be connected between pins sbp and sbm v dda 16 analog supply voltage for the dc/dc converter sbm 17 capacitors connection for the dc/dc converter; a 220 nf capacitor with esr < 100 m w must be connected between pins sbp and sbm agnd 18 analog ground connection for the dc/dc converter sam 19 capacitors connection for the dc/dc converter; a 220 nf capacitor with esr < 100 m w must be connected between pins sap and sam v dd 20 power supply voltage scl 21 serial clock input of the i 2 c-bus (open drain) sda 22 serial data input/output of the i 2 c-bus (open drain) sad0 23 i 2 c-bus address selection input 0 sad1 24 i 2 c-bus address selection input 1 irq 25 interrupt request output to host (open drain; active low) clkin1 26 external clock input for card 1 i/o1uc 27 i/o connection to host for card 1; internal 22 k w pull-up resistor to v ddi i/o2uc 28 i/o connection to host for card 2; internal 22 k w pull-up resistor to v ddi clkin2 29 external clock input for card 2 c del 30 delay capacitor connection for the voltage supervisor (1 ms per 2 nf) v ddi 31 interface signals reference supply voltage i/o1 32 i/o contact to card 1 (c7 contact); internal 15 k w pull-up resistor to v cc1 2001 aug 15 6 philips semiconductors product speci?cation dual smart card interface TDA8020hl handbook, full pagewidth TDA8020hl fce833 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 pres1 cgnd1 clk1 v cc1 rst1 i/o2 pres2 cgnd2 sad1 clk2 v cc2 rst2 gnd v up sap sbp v dda sad0 sda scl v dd sam agnd sbm irq clkin1 i/o1uc i/o2uc clkin2 c del v ddi i/o1 fig.2 pin configuration. 2001 aug 15 7 philips semiconductors product speci?cation dual smart card interface TDA8020hl functional description throughout this specification, it is assumed that the reader is familiar with iso 7816 norm terminology. supply the TDA8020hl operates with a supply voltage from 2.5 to 6.5 v. an integrated voltage supervisor ensures that no spike appears on cards contacts during power-on or off. the supervisor also initializes the device, and forces an automatic emergency deactivation of the contacts in the event of a supply drop-out. as long as the supply voltage is below the threshold voltage v th1 , the capacitor c del remains uncharged. when the supply voltage reaches v th1 and v hys1 , then c del is charged with a small current source of approximately 2 m a. when the voltage on c del reaches v th2 , then the supervisor is no longer active. as long as the supervisor is active (pin irq is low), bit supl in the status register is set. when pin irq goes high the supervisor becomes inactive (see fig.3). separate supply pins are used for the dc/dc converter, allowing specific decoupling for counteracting the noise the switching transistors may induce on the supply. a specific reference supply voltage, v ddi , is used for the interface signals clkin1, clkin2, i/o1uc, i/o2uc, sad0, sad1, scl, sda and irq, which can be lower than v dd (minimum 1.5 v), thus allowing direct control with a low voltage supplied device. pins scl, sda and irq are open-drain outputs, and may be externally pulled up to a voltage higher than v dd . i 2 c-bus a 400 khz i 2 c-bus slave interface is used for configuring the device and reading the status. the bus has 2 addresses, one for each card. 4 devices may be used in parallel due to the address selection pins sad0 and sad1 (see table 1). table 1 proposed addresses pin sad1 pin sad0 card 1 card 2 low low 40h 48h low high 42h 4ah high low 44h 4ch high high 46h 4eh handbook, full pagewidth t w t w fce835 bus ok bus not responding bus not responding bus not responding bus ok status read after event v dd v th1 + v hys1 v th1 v th2 v cdel irq fig.3 supply supervisor. 2001 aug 15 8 philips semiconductors product speci?cation dual smart card interface TDA8020hl w riting commands start, address, write, control byte, stop. table 2 control bits (all bits cleared after power-on) name bit description start/ st op 0 when set, initiates an activation and a cold reset procedure; when reset, initiates a deactivation sequence warm 1 when set, initiates a warm reset procedure; automatically reset by hardware when the card starts answering or when the card is declared mute 3 and 5 v 2 when set, v cc = 3 v; when reset, v cc =5v pdown 3 when set, the con?guration de?ned by bit clkpd is applied on pin clk, and the circuit enters the power-down mode; when reset, the circuit goes back to normal (active) mode clkpd 4 when set, clk is stopped high during power-down mode; when reset, clk is stopped low in power-down mode clksel1 5 bits 5 and 6 determine the clock to the card in normal mode according to table 3 clksel2 6 i/oen 7 when set, i/o is transferred on i/ouc; when reset, i/o to i/ouc is high-impedance when deactivating the card, by resetting the start bit, only bit 0 must be changed. the clock to the cards in active mode is selected with bits clksel1 and clksel2; see table 3. table 3 selecting the card clock. all frequency changes are synchronous, thus ensuring that no pulse is shorter than 45% of the smallest period. for cards power reduction modes, clkin may be stopped after switching to stop low or stop high. clkin should be restarted before leaving this mode. a correct duty factor can not be guaranteed in the clkin configuration, as it depends on the duty factor of the clkin signal. bit clksel2 bit clksel1 clock output 0 0 clkin/8 0 1 clkin/4 1 0 clkin/2 1 1 clkin 2001 aug 15 9 philips semiconductors product speci?cation dual smart card interface TDA8020hl r eading status start, address, read, status byte, stop. table 4 status bits (all bits cleared after power-on, except supl and pres) when one of the bits presl, mute, early and prot is set, then pin irq goes low until the status byte has been read. after power-on, bit supl is set until the status byte has been read, and pin irq is low until the supervisor becomes inactive. name bit description pres 0 set when the card is present; reset when the card is not present presl 1 set when the card has been inserted or extracted; reset when the status has been read i/o 2 set when i/o is high and reset if i/o is low supl 3 set when the supervisor has signalled a fault; reset when the status has been read prot 4 set when an overload or an overheating has occurred during a session; reset when the status has been read mute 5 set during atr when the selected card has not answered during the iso 7816 time slots early 6 set during atr when the selected card has answered too early active 7 set if the card is active; reset if the card is inactive dc/dc converter v cc1 is the supply voltage for card 1 contacts, v cc2 for card 2 contacts. card 1 and card 2 may be independently powered-down, powered at 5 v or powered at 3 v. a capacitor type step-up converter is used for generating these voltages. this step-up converter acts either as a doubler, tripler or follower. if v cc is the maximum value of v cc1 and v cc2 , then there are 4 possible situations: v dd = 3 v and v cc = 3 v: in this case, the dc/dc converter acts as a doubler with a regulation of approximately 4.0 v v dd = 3 v and v cc = 5 v: in this case, the dc/dc converter acts as a tripler with a regulation of approximately 5.5 v v dd = 5 v and v cc = 3 v: in this case, the dc/dc converter acts as a follower: v dd is applied on v up v dd = 5 v and v cc = 5 v: in this case, the dc/dc converter acts as a doubler with a regulation of approximately 5.5 v. the switch between the modes is automatically executed when v dd is approximately 3.4 v. each card may independently draw a current up to 65 ma, also during activation, with a supply voltage from 2.5 v up to 6.5 v provided the sum of i cc1 and i cc2 does not exceed 80 ma. if v dd > 3 v, for 5 v cards, then both cards can draw up to 55 ma at the same time. if v dd > 3.3 v, for 3 v cards, then both cards can draw up to 50 ma at the same time. the dc/dc converter is powered with specific pins (v dda and agnd) to enable separate decoupling. the output voltage, v up , is internally fed to the v cc generators. v cc1 ,v cc2 and cgnd1, cgnd2 are used as a reference for all other cards contacts. sequencers and clock counter two sequencers are used to ensure activation and deactivation sequences according to iso 7816 and emv norms, even in the event of an emergency (card removal during transaction, supply drop-out and hardware problem). the sequencers are clocked by the internal oscillator. the activation of a card is initiated by setting the card select bit and the start bit within the control register. this is only possible if the card is present and if the voltage supervisor is not active. during activation the dc/dc converter is initiated (except if another card is already powered up or if v dd = 5 v and v cc = 3 v). v cc then goes high to the selected voltage (3 or 5 v), the i/o lines are then enabled and the clock is started with rst low. 2001 aug 15 10 philips semiconductors product speci?cation dual smart card interface TDA8020hl if a start bit is detected on the i/o during the first 200 clk pulses, then it is omitted. if a start bit is detected between 200 and 352 clk pulses, then bit early is set in the status register. if the card starts answering before 41950 clk pulses, then rst remains low level. if not, after 41950 clk pulses, rst is toggled high. if, again, a start bit is detected within 352 clk pulses, bit early is set in the status register. if the card does not answer before 41950 new clk pulses, then bit mute is set in the status register. if the card answers within the correct window, then the clk count is stopped and the system controller may send commands to the card. deactivation is initiated either by the system controller (reset bit start), or automatically in the event of a hardware problem or supply drop-out. with a supply drop-out both cards are deactivated at the same time. during deactivation, rst goes low, the clock is stopped and the i/o lines go low. v cc then goes low with a controlled slope and the dc/dc converter is stopped if no card is active. outside a session, cards contacts are forced low impedance to cgnd. activation sequence when the cards are inactive, v cc , clk, rst and i/o are low, with low impedance with respect to cgnd. the dc/dc converter is stopped. when everything is satisfactory (voltage supply, card present and no hardware problems), the system controller may initiate an activation sequence of a present card (see fig.4): the dc/dc converter is started (t1). if one card was already active, then the dc/dc converter was already on, and nothing more occurs at this step v cc starts rising from 0 to 5 or 3 v with a controlled rise time of 0.14 v/ m s typical (t2) i/o rises to v cc (t3); internal 10 k w pull-up resistors to v cc clk is sent to the card and rst is enabled (t4 = t act ). if the card does not answer within the first 41950 clk cycles, then rst is raised high (t5). the sequencer is clocked by f int /64 which leads to a time interval t of 25 m s typical. thus t1 = 0 to t/64; t2 = t1 + 3t/2; t3 = t1 + 7t/2 and t4 = t1 + 4t. v up v cc i/o clk rst handbook, full pagewidth start/stop t0 t1 t2 t3 t4 t5 fce837 atr fig.4 activation sequence. t4=t act . 2001 aug 15 11 philips semiconductors product speci?cation dual smart card interface TDA8020hl deactivation sequence when the session is completed, the microcontroller resets bit start/ stop to logic 0 (t10). the circuit then executes an automatic deactivation sequence (see fig.5): card reset (rst falls low) (t11) clk is stopped (t12) i/o falls to 0 v (t13) v cc falls to 0 v with typical 0.14 v/ m s slew rate (t14) the dc/dc converter is stopped (if both cards are inactive) and clk, rst, v cc and i/o become low impedance to cgnd (t15). t11 = t10 + t/64; t12 = t11 + t/2; t13 = t11 + t; t14 = t11 + 3t/2; t15 = t11 + 7t/2. the deactivation time t de is the time that v cc needs to drop below 0.4 v from start/ stop to logic 0 (t10). handbook, full pagewidth t de t10 t11 t12 t13 t14 t15 v up v cc i/o clk rst start/stop fce836 fig.5 deactivation sequence. 2001 aug 15 12 philips semiconductors product speci?cation dual smart card interface TDA8020hl protections the current on pin clk is limited to 70 ma. the current on pin rst is limited to 20 ma; if the current reaches this value with rst low, then an emergency deactivation sequence is performed, irq is pulled low and bit prot is set in the status register. the current on pins i/o is limited to +15 and - 15 ma. the current on v cc is limited to 90 ma; if i cc reaches this value, then an emergency deactivation sequence is performed, irq is pulled low and bit prot is set in the status register. in the event of overcurrent on v cc , card take-off during a session, overheating, or overcurrent on rst, then the TDA8020hl performs an automatic emergency deactivation sequence on the corresponding card, resets bit start/ stop and pulls pin irq low. in the event of overheating or supply drop-out, the TDA8020hl performs an automatic emergency deactivation sequence on both cards, resets both bits start/ stop and pulls pin irq low. clock inputs and data inputs/outputs to the system controller clkin1 is the input clock for card 1, clkin2 for card 2. they may be driven separately from the system controller, or be tied together externally and driven with the same signal. an rc filter is needed on these lines in order to limit the influence of possible fast transitions. i/o1uc is the data signal to or from card 1, i/o2uc to or from card 2. they can be driven separately from the system controller, in which case both bits i/oen may be set to logic 1. they can also be driven by the same signal, in which event they have to be tied together externally, but each bit i/oen has to be set or reset according to the addressed card. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min. max. unit v dd supply voltage on pins v dd and v dda - 0.5 +6.5 v v ddi supply voltage for interface signals - 0.5 +6.5 v v n input voltage on pins sap, sam, sbp, sbm and v up - 0.5 +7.5 v on all other pins - 0.5 v dd + 0.5 v i n dc current from or to pins sap, sam, sbp, sbm and v up - 200 +200 ma from or to all other pins - 5+5ma p tot total power dissipation t amb = - 20 to +85 c - 460 mw t stg storage temperature - 55 +150 c t j junction temperature - 125 c v es electrostatic discharge voltage on pins i/o1, v cc1 , rst1, clk1, cgnd1, pres1, i/o2, v cc2 , rst2, clk2, cgnd2 and pres2 - 6+6kv on all other pins - 2+2kv 2001 aug 15 13 philips semiconductors product speci?cation dual smart card interface TDA8020hl thermal characteristics characteristics v dd = 3.3 v; v ddi = 1.5 v; f clkin1 =f clkin2 = 10 mhz; gnd = 0 v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 80 k/w symbol parameter conditions min. typ. max. unit temperature t amb ambient temperature - 25 - +85 c supply v dd supply voltage on pins v dd and v dda 2.5 - 6.5 v i dd supply current (i dd and i dda ) inactive mode -- 150 m a power-down mode; 2 cards activated; v cc1 =v cc2 =5v; i cc1 =i cc2 = 100 m a; clk1 and clk2 stopped -- 2.5 ma active mode; v cc1 =v cc2 =5v; i cc1 +i cc2 = 80 ma; clk1 = clk2 = 5 mhz -- 400 ma active mode; v cc1 =v cc2 =3v; i cc1 =i cc2 = 10 ma; clk1 = clk2 = 5 mhz -- 80 ma v ddi supply voltage for interface signals 1.5 - v dd v i ddi supply current for interface signals -- 120 m a v th1 threshold voltage on v dd falling 2.1 - 2.4 v v hys1 hysteresis on v th1 50 - 100 mv v th2 threshold voltage on pin c del - 1.38 - v v cdel voltage on pin c del -- v dd + 0.3 v i cdel output current at pin c del pin grounded (charge) -- 2 -m a v cdel =v dd (discharge) - 5 - ma t w width of the internal alarm pulse c del =22nf - 10 - ms dc/dc converter f int internal oscillator frequency 2 2.5 3 mhz v up voltage on pin v up at least one 5 v card - 5.5 - v both cards 3 v - 4 - v v dt detection voltage for doubler, tripler and follower selection - 3.4 - v 2001 aug 15 14 philips semiconductors product speci?cation dual smart card interface TDA8020hl card supply voltages (pins v cc1 and v cc2 ); note 1 v o(inactive) output voltage in inactive mode no load 0 - 0.1 v i inactive = 1 ma 0 - 0.3 v i inactive current from v cc when inactive pin grounded --- 1ma v cc(ripple) output voltage including ripple active mode; i cc < 65 ma; 5 v card; i cc1 +i cc2 < 80 ma; 2.5v 2001 aug 15 15 philips semiconductors product speci?cation dual smart card interface TDA8020hl clock output to the cards (pins clk1 and clk2) v o(inactive) output voltage in inactive mode no load 0 - 0.1 v i inactive = 1 ma 0 - 0.3 v i inactive current from pin clk when inactive pin grounded 0 -- 1ma v ol low-level output voltage i ol = 200 m a0 - 0.3 v v oh high-level output voltage i oh < - 200 m av cc - 0.5 - v cc v t r rise time c l =30pf -- 8ns t f fall time c l =30pf -- 8ns f clk clock frequency 1 mhz idle con?guration 1 - 1.5 mhz operational 0 - 10 mhz d duty factor c l =30pf 45 - 55 % sr slew rate (rise and fall) c l =30pf 0.2 -- v/ns data lines (pins i/o1 and i/o2); note 2 v o(inactive) output voltage in inactive mode no load 0 - 0.1 v i inactive =1ma -- 0.3 v i inactive current from pin i/o when inactive pin grounded --- 1ma v ol low-level output voltage i ol =1ma 0 - 0.3 v v oh high-level output voltage no dc load 0.9v cc - v cc + 0.1 v i oh < - 20 m a 0.8v cc - v cc + 0.1 v i oh < - 40 m a 0.75v cc - v cc + 0.1 v i edge current from pins i/o1 and i/o2 when active pull-up v oh = 0.9v cc ; c l =80pf - 1 -- ma t d(edge) delay between falling edge on pins i/o1, i/o2, i/o1uc, i/o2uc and width of active pull-up pulse - 500 650 ns v il low-level input voltage - 0.3 - +0.8 v v ih high-level input voltage 1.5 - v cc v i il low-level input current on pin i/o v il =0 -- 600 m a i lih high-level input leakage current on pin i/o v ih =v cc -- 10 m a t i(r) ,t i(f) input transition times from v il(max) to v ih(min) -- 1.5 m s t o(r) ,t o(f) output transition times c l < 80 pf; no dc load; 10% to 90% from 0 to v cc1 and v cc2 -- 0.1 m s c i input capacitance on pins i/o1 and i/o2 -- 10 pf r pu(int) internal pull-up resistance between pin i/o and v cc 12 15 18 k w symbol parameter conditions min. typ. max. unit 2001 aug 15 16 philips semiconductors product speci?cation dual smart card interface TDA8020hl f max maximum frequency on pins i/o1 and i/o2 -- 500 khz data lines (pins i/o1uc and i/o2uc); note 3 v ol low-level output voltage i ol =1ma 0 - 0.4 v v oh high-level output voltage no dc load 0.9v ddi - v ddi + 0.2 v i oh < - 10 m a 0.75v ddi - v ddi + 0.2 v v il low-level input voltage - 0.3 - 0.25v ddi v v ih high-level input voltage 0.7v ddi - v ddi + 0.3 v i il low-level input current v il =0 -- 600 m a i lih high-level input leakage current v ih =v ddi -- 10 m a t i(r) , t i(f) input transition times from v il(max) to v ih(min) -- 1 m s t o(r) , t o(f) output transition times c l < 30 pf; 10% to 90% from 0tov ddi -- 0.1 m s r pu(int) internal pull-up resistance between i/o1uc, i/o2uc and v ddi 15 22 30 k w timing t act activation sequence duration -- 135 m s t de deactivation sequence duration -- 110 m s protections and limitations i cc(sd) shutdown and limitation current at v cc1 and v cc2 -- 90 - ma i i/o(lim) limitation current on pins i/o1 and i/o2 - 15 - +15 ma i clk(lim) limitation current on pins clk1 and clk2 - 70 - +70 ma i rst(sd) shutdown and limitation current on pins rst1 and rst2 - 20 - +20 ma t j(sd) shutdown die temperature - 150 - c card presence inputs (pins pres1 and pres2) v il low-level input voltage -- 0.3v dd v v ih high-level input voltage 0.7v dd -- v i lil low-level input leakage current v i =0 -- 20 m a i lih high-level input leakage current v i =v dd -- 20 m a symbol parameter conditions min. typ. max. unit 2001 aug 15 17 philips semiconductors product speci?cation dual smart card interface TDA8020hl notes 1. two ceramic multilayer capacitors of minimum 100 nf with low esr should be used in order to meet these speci?cations. 2. pin i/o1 has an internal 15 k w pull-up resistor to v cc1 and pin i/o2 has an internal 15 k w pull-up resistor to v cc2 . 3. pins i/o1uc and i/o2uc have an internal 22 k w pull-up resistor to v ddi . clock inputs (pins clkin1 and clkin2) f ext external frequency applied on clkin1 and clkin2 0 - 25 mhz v il low-level input voltage 0 - 0.25v ddi v v ih high-level input voltage 0.7v ddi - v ddi + 0.3 v t i(r) , t i(f) input transition times -- 100 ns logic inputs (pins sad0 and sad1) v il low-level input voltage - 0.3 - 0.25v ddi v v ih high-level input voltage 0.7v ddi - v ddi + 0.3 v i lil low-level input leakage current -- 20 m a i lih high-level input leakage current -- 20 m a c i input capacitance -- 10 pf interrupt line (pin irq; open-drain; active low output) v ol low-level output voltage i o =2ma -- 0.3 v i lh high-level leakage current -- 10 m a serial data input/output (pin sda; open-drain) v il low-level input voltage - 0.3 - 0.25v ddi v v ih high-level input voltage 0.7v ddi - v ddi + 0.3 v i lh high-level leakage current -- 1 m a i il low-level input current depends on the pull-up resistance --- v ol low-level output voltage i ol =3ma -- 0.3 v serial clock input (pin scl; open-drain) v il low-level input voltage - 0.3 - 0.25v ddi v v ih high-level input voltage 0.7v ddi - v ddi + 0.3 v i lh high-level leakage current -- 1 m a i il low-level input current depends on the pull-up resistance --- symbol parameter conditions min. typ. max. unit 2001 aug 15 18 philips semiconductors product speci?cation dual smart card interface TDA8020hl this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... application information a ndbook, full pagewidth 220 w 1.5 to 6.5 k w 1 k w microcontroller 100 k w 100 k w 0 k w 100 nf card_read_lm01 card 2 + 3.3 v + 1.5 v + 1.5 v + 1.5 to + 6.5 v + 1.5 v + 3.3 v + 3.3 v 10 m f (16 v) 10 m f 100 nf 10 m f (16 v) 100 nf 33 m f (16 v) 100 nf 220 nf 22 nf 220 nf 220 nf 10 pf 100 nf 100 nf 33 pf 14.745 mhz 33 pf 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 p0_0 v cc p0_1 p0_2 p0_3 p0_4 p0_5 p0_6 p0_7 ea ale psen p2_7 p2_6 p2_5 p2_4 p2_3 p2_2 p2_1 p2_0 p1_0 p1_1 p1_2 p1_3 p1_4 p1_5 p1_6 p1_7 rst p3_0 p3_1 p3_2 p3_3 p3_4 p3_5 p3_6 p3_7 xtal2 xtal1 v ss c4 c3 c2 c1 c5i c6i c7i c8i c8 c7 c6 c5 c1i c2i c3i c4i k1 k2 TDA8020hl fce838 1 2 3 4 5 6 7 8 9 10111213141516 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 pres1 cgnd1 clk1 v cc1 rst1 i/o2 pres2 cgnd2 sad1 clk2 v cc2 rst2 gnd v up sap sbp v dda sad0 sda scl v dd sam agnd sbm irq clkin1 i/o1uc i/o2uc clkin2 c del v ddi i/o1 100 k w 0 k w 100 nf card_read_lm01 card 1 + 3.3 v c4 c3 c2 c1 c5i c6i c7i c8i c8 c7 c6 c5 c1i c2i c3i c4i k1 k2 fig.6 application diagram. 2001 aug 15 19 philips semiconductors product speci?cation dual smart card interface TDA8020hl package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.60 0.20 0.05 1.45 1.35 0.25 0.4 0.3 0.18 0.12 7.1 6.9 0.8 9.15 8.85 0.9 0.5 7 0 o o 0.25 0.1 1.0 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot358 -1 136e03 ms-026 99-12-27 00-01-19 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.9 0.5 d b p e q e a 1 a l p detail x l (a ) 3 b 8 c d h b p e h a 2 v m b d z d a z e e v m a x 1 32 25 24 17 16 9 y pin 1 index w m w m 0 2.5 5 mm scale lqfp32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm sot358-1 2001 aug 15 20 philips semiconductors product speci?cation dual smart card interface TDA8020hl soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 2001 aug 15 21 philips semiconductors product speci?cation dual smart card interface TDA8020hl suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. package soldering method wave reflow (1) bga, hbga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable data sheet status (1) product status (2) definitions objective data development this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a. 2001 aug 15 22 philips semiconductors product speci?cation dual smart card interface TDA8020hl definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011. 2001 aug 15 23 philips semiconductors product speci?cation dual smart card interface TDA8020hl notes ? koninklijke philips electronics n.v. 2001 sca73 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 753504/02/pp 24 date of release: 2001 aug 15 document order number: 9397 750 08605 |
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